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VERILOG
views 27
,
size 720 b
module ALU (A, B, sel, Y, Negative, Zero);
	input [32 - 1:0] A, B;
	output reg [32 - 1:0] Y;
	input [2:0] sel;
	output reg Negative, Zero;

    always@(*) begin
        case (sel)
            3'b000 : Y = 32'b0;
            3'b001 : Y = A & B;
            3'b010 : Y = A | B;
            3'b011 : Y = A ^ B;
            3'b100 : Y = ~ A;
            3'b101 : Y = A - B;
            3'b110 : Y = A + B;
            3'b111 : Y = A << 1'b1;
        endcase

        if (Y === 32'b0)
            assign Zero = 1'b1;
        else
            assign Zero = 1'b0;

        if (Y[31] === 1'b1)
            assign Negative = 1'b1;
        else
            assign Negative = 1'b0;
    end

endmodule
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